`timescale 1ns / 1ps
//
// CSE141L Lab 2, Part 1: Fetch Datapath
// University of California, San Diego
//
// Written by Tiffany Jaya A06919807, 5/3/2011
// Written by Arthur Lee A07899759, 5/3/2011

// inst_mux unit module
//
// parameters:
//      I_WIDTH: instruction width
//      A_WIDTH: SRAM address width
//      O_WIDTH: offset width in a branch instruction (2's complement)
//

module inst_mux#(parameter I_WIDTH = 17, A_WIDTH = 10, O_WIDTH = 5)
(
    input   clk,

	 input [0:O_WIDTH-1] selector,
	
    // instructions (23)
    input   i_data,
    input   i_address,
    input   i_valid
);

endmodule